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-1 - nju6538 ver.2003-05-09 1/8, 1/9, 1/10 duty bitmap lcd driver with key scan general description the nju6538 is a 10-common x 65-segment bitmap lcd driver to display graphics or characters. it contains 650 bits display data ram, microprocessor interface circuit, common and segment drivers, key scan circuit, and general output ports. an image data from mpu through the serial interface is stored into the 650 bits internal displayed on the lcd panel through the commons and segments drivers. the nju6538 displays 10 x 65 dots graphics or 11-character 1-line by 5 x 7 dots character + 3 x 65 dots icons. it contains key scan circuit transmitting the 25-keys maximum (5 x 5 = 25) to mpu. also it provides 4 general purpose output ports with pwm output function maximum to drive leds or others directly. furthermore, the nju6538 can select a lcd driving voltage out of 16 steps voltage by the instruction adjust the display contrast of lcd panel. features direct correspondence between display data ram and lcd pixel display data ram : 650-bits lcd drivers : 65-seg, 10-com serial interface (sio, scl, cs) programmable duty ratio 1/8 duty 7-common x 65-segment + 1-icon common 1/9 duty 7-common x 65-segment + 2-icon common 1/10duty 7-common x 65-segment + 3-icon common bias ratio 1/4 bias 25-key scan function (5 x 5 matrix) needless for anti-reverse current diodes in key scan general output ports with 128-steps pwm output (possible led driving) maximum 4-ports useful instruction set display on/off, page address set, column address set, display data write, adc select, inverse display on/off, whole display on/off, reset, evr register set, duty select, power save mode set, general output port pwm phase / frequency set, general output port pwm data set, general output port / key scan output select bleeder resistance on-chip software contrast control (16 steps) operating voltage logic operating voltage 2.7 to 5.5v lcd driving voltage 5.0 to 10.0v package outline qfp100-g1 qfp100-c2 c-mos technology (substrate: p) preliminary package outline NJU6538FC2 nju6538fg1
- 2 - nju6538 ver.2003-05-09 pin configration seg 48 seg 47 seg 46 seg 45 seg 44 seg 43 seg 42 seg 41 seg 40 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 31 seg 30 seg 29 scl sio seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 28 s 0 /po 3 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k 4 v dd vlcd 1 vlcd 2 v 0 v 1 v 2 v ss osc resb ce po 2 po 1 po 0 com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com 1 seg 65 seg 64 seg 63 seg 62 seg 61 seg 60 seg 59 seg 58 seg 57 seg 56 seg 55 seg 54 seg 53 seg 52 seg 51 seg 50 seg 49 NJU6538FC2 seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 seg 43 seg 42 seg 41 seg 40 seg 39 seg 38 seg 37 seg 36 seg 35 seg 34 seg 33 seg 32 seg 31 seg 30 seg 29 seg 28 seg 27 seg 26 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com 1 seg 65 seg 64 seg 63 seg 62 seg 61 seg 60 seg 59 seg 58 seg 57 seg 56 seg 55 seg 54 seg 53 seg 52 seg 51 nju6538fg1 po 0 po 1 po 2 s 0 /po 3 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k 4 v dd vlcd 1 vlcd 2 v 0 v 1 v 2 v ss osc resb ce scl sio
-3 - nju6538 ver.2003-05-09 block diagram e.v.r. vlcd2 v0 v1 vss common driver segment driver com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 seg63 seg64 seg65 display data ram instruction data buffer instruction decoder key data buffer key scan control serial i/f k0 k1 k2 k3 k4 ce scl sio oscillator reset osc seg1 seg2 seg3 vlcd1 v2 s4 s3 s2 s1 po3/s0 po2 po1 po0 general output driver power on reset resb reset timing generator column address decoder page address decoder input buffer
- 4 - nju6538 ver.2003-05-09 terminal description no. fg1 fc2 symbol i/o description 1 to 65 3 to 67 seg 1 to seg 65 o segment output terminal. 66 to 72 68 to 74 com 1 to com 7 o common output terminal. 73 to 75 75 to 77 com 8 to com 10 o icon common output terminal. 76 to 78 78 to 80 po0 to po2 o general output port 128-step pwm waveform output by mpu control. 79 81 po3/s 0 o general output port / key scanning input terminal select general output port or key scanning input terminal by the instruction. a function must be selected either po3 or s 0 general output port 128-step pwm waveform output by mpu control. key scanning input terminals (no need for anti-reverse current diode in key scan) 80 to 83 82 to 85 s 1 to s 4 o key scanning input terminals. (no need for anti-reverse current diode in key scan) 84 to 88 86 to 90 k 0 to k 4 i key scanning input terminals. (with internal pull-down resistor) 89 91 v dd - power supply terminal.( 2.7v to 5.5v) 90 92 vlcd1 i lcd driving voltage input terminal. 91 92 93 94 93 94 94 96 vlcd2 v 0 v 1 v 2 i lcd driving voltage stabilization capacitor terminals. connect the capacitor between each terminal and vss. 95 97 v ss - ground terminal. 96 98 osc i/o osclator terminal. conect the external resistor. 97 99 resb i reset terminal. (with internal pull-up resistor) in case of only power-on reset should be open. 98 100 ce i chip enable terminal 99 1 scl i serial clock input terminal 100 2 sio i/o serial data input or output terminal
-5 - nju6538 ver.2003-05-09 functional description (1) description for each blocks (1-1) serial i/f the serial i/f controls serial data from external data. (1-2) instruction data buffer the instruction data buffer stores instruction code from external. (1-3) instruction decoder the instruction decoder decodes instruction code and controls each blocks. (1-4) display data ram the display data ram stores data for display from mpu. (1-5) segment driver the segment driver generates driving waveform to segment terminal on display data. (1-6) general output driver the general output driver generates output signal level to general output terminal on output data. (1-7) common driver the common driver generates driving waveform to common terminal. (1-8) electrical variable resistance (e.v.r.) the electrical variable resistance adjusts lcd driving voltage from v0 to v2. (1-9) key scan controller the key scan controller controls to input from external key data. (1-10) key data buffer the data buffer for key stores key data until next key data is stored. (1-11) cr oscillator the oscillator is external connect resistor, which generates the master clock. (1-12) reset circuit the reset circuit is type of detectable voltage. it resets internal circuit when the power turns on or drop the voltage. fig.1 display data ram (ddram) map page address data display pattern common drivers d0 j j com1 d1 j j com2 d2 j j j com3 d3 j j j com4 d4 j j j com5 d5 j j com6 d0=?0? d6 j j page 0 com7 d0 com8 d1 com9 d0=?1? d2 page 1 com10 d0="0" 00 01 02 03 04 05 06 3f 40 column address adc d0="1" 40 3f 3e 3d 3c 3b 3a 01 00 segment drivers 1 2345 6 7 - - - - - - - - - - - - - - - - 64 65
- 6 - nju6538 ver.2003-05-09 (2) instruction 3-wired serial i/f is clock synchronized of the scl clock. and d 7 to d 0 signal select data or instruction by a0 signal. the data input as msb(d7) first serially. table 1. instruction code (*: don?t care) code instruction a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description (a) display on/off 0 1 0 1 0 1 1 1 0/1 lcd display on / off d 0 =0 : off, d 0 =1 : on (b) page address set 0 1 0 1 1 0 0 0 0/1 set the page of ddram to the page address registor. d 0 =0 : page 0, d 0 =1 : page 1 culumn address set higher order 3-bits 0 0 0 0 1 * higher order column add. set the higher order 3 bits column address to rhe registor. (c) culumn address set lower order 4-bits 0 0 0 0 0 lower order column add. set the lower order 4 bits column address to rhe registor. (d) display data write 1 * write data write the data into the display data ram(ddram) (e) adc select 0 1 0 1 0 0 0 0 0/1 set the ddram to seg driver d 0 =0 : nomal, d 0 =1 : inverse (f) inverse display on / off 0 1 0 1 0 0 1 1 0/1 inverse lcd display on / off d 0 =0 : nomal, d 0 =1 : inverse (g) whole display on / normal display 0 1 0 1 0 0 1 0 0/1 whole display tern on d 0 =0: normal, d 0 =1: whole display (h) reset 0 1 1 1 0 0 0 1 0 initialize the internal circuit (i) e.v.r. register set 0 0 0 1 0 e.v.r. data set the contrast control e.v.r. (16 steps) (j) duty select 0 0 0 1 1 0 duty duty set (1/8,1/9,1/10) (d 2 ,d 1 ,d 0 )=( 0,0,0) : 1/8duty (d 2 ,d 1 ,d 0 )=( 0,0,1) : 1/9 duty (d 2 ,d 1 ,d 0 )=( 0,1,0) : 1/10 duty (k) power save mode set 0 0 1 0 0 0 0 power save set the power save mode (d 1 ,d 0 )=(0,0) : nomal (d 1 ,d 0 )=(0,1) : power save 1 (d 1 ,d 0 )=(1,0) : power save 2 (d 1 ,d 0 )=(1,1) : power save 3 (l) general output port pwm phase / freqency set 0 0 1 0 1 0 0 phase freq. set the pwm phase / freqency d 1 : pwm phase set d 0 : pwm freqenccy set general output port serect 0 0 1 1 0 0 0 port select the general output port for pwm level set general output port pwm set high order 3-bits / pwm enable set 0 1 0 0 0 pwmen high order pwm data pwmen=0:?l? output pwmen=1:pwm output set the higher order 3 bits pwm data to rhe registor. (m) general output port pwm set lower order 4-bits 0 0 1 1 1 lower order pwm data set the lower order 4 bits pwm data to rhe registor. (n) general output port / key scan output select 0 1 0 0 1 0 0 0 0/1 select general output port or key scan output select by po3/s 0 terminal d 0 =0 : general output port d 0 =1 : key scan output (o) maker test 0 1 1 1 1 test data do not use this instruction.
-7 - nju6538 ver.2003-05-09 (2-1) instruction discription (a) display on / off this instruction selects display turn-on or turn-off regardless of the contents of the ddram. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 1 d d 0: display off 1: display on (b) page address set in order to access to the ddram for writing or reading display data, both ?page address set? and ?column address set? instructions are required before accessing. the page address ?0? should be used for icon display because the only d 0 to d 6 is valid. the page address ?1? should be used for icon display because the only d 0 to d 2 is valid. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 0 0 0 a 0 a 0 page 0 0 1 1 (c) column address set as above-mentioned, in order to access to the ddram for writing or reading display data, it is necessary to execute both ?page address set? and ?column address set? before accessing. the 8-bit column address data will be valid when both upper 3-bit and lower 4-bit data are set into the column address register. once the column address is set, it will automatically increment (+1) whenever the ddram will be accessed, so that the ddram will be able to be continuously accessed without ?column address set? instruction. the column address will stop increment and the page address will not be changed when the last address (40)h is addressed. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 1 * a 6 a 5 a 4 upper 4-bit 0 0 0 0 0 a 3 a 2 a 1 a 0 lower 4-bit a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address (hex) 0 0 : : 1 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 1 : : 0 00 01 : : 40
- 8 - nju6538 ver.2003-05-09 (d) display data write this instruction writes display data into the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without ?column address set? instruction. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 * write data *:don ? t care (e) adc select this instruction selects segment driver direction. the correspondence between the column address and segment driver direction is shown in fig.1. segment driver output order is inverse, when this instruction executes, therefore, the placement nju6538 against the lcd panel becomes easy. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 0 d d 0: clokwise output(normal) s 1 s 65 1: counterclockwise output(inverse) s 65 s 1 (f) inverse display on / off this instruction inverses the status of turn-on or turn-off of entire lcd pixels. it doesn?t change the contents of the ddram. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 1 1 d d 0: normal ram data ?1? correspond to ?on? 1: inverse ram data ?0? correspond to ?on? (g) whole display on this instruction turns on entire lcd pixels regardless the contents of the ddram. it doesn?t change the contents of ddram. this instruction executed prior to the ?normal or inverse display on/off set? instruction. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 1 0 d d 0: normal display (whole display off) 1: whole display turns on (whole display on)
-9 - nju6538 ver.2003-05-09 (h) reset this instruction reset the lsi to the following status, however it doesn?t change the contents of the ddram. please be careful that it can?t be substituted for the reset operation by using of the resb terminal. reset status by ?reset? instruction: 1. page address : (0) page 2. column address : (00) h 3. evr register : (d 3 , d 2 , d 1 , d 0 = ?1, 1, 1, 1?) 4. duty select :1/10 duty 5. general output port(po0 to po3) pwm phase / frequency (d 1 ,d 0 = ?0,0?) 6. general output port(po0 to po3) pwmen=0, pwm value (pwm 6 , pwm 5 , pwm 4 , pwm 3 , pwm 2 , pwm 1 , pwm 0 = ? 0,0,0,0,0,0,0?) 7. set the general output port (po3) by po3/s0 terminal the ddram is not affected by this initialization. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 1 1 0 0 0 1 0 (i) evr register set e.v.r. resister set instruction adjusts the contrast of the lcd, and selects. one lcd driving voltage vlcd out of 16 voltage-stages by setting e.v.r. register. set the binary code ?0000? when contrast adjustment is unused. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 0 e.v.r. data d 3 d 2 d 1 d 0 v lcd2 terminal level (typical) 0 0 0 0 v lcd1 0 0 0 1 0.984v lcd1 0 0 1 0 0.968v lcd1 0 0 1 1 0.952v lcd1 0 1 0 0 0.938v lcd1 0 1 0 1 0.923v lcd1 0 1 1 0 0.909v lcd1 0 1 1 1 0.896v lcd1 1 0 0 0 0.882v lcd1 1 0 0 1 0.870v lcd1 1 0 1 0 0.857v lcd1 1 0 1 1 0.845v lcd1 1 1 0 0 0.833v lcd1 1 1 0 1 0.822v lcd1 1 1 1 0 0.811v lcd1 1 1 1 1 0.800v lcd1
- 10 - nju6538 ver.2003-05-09 (j) duty select duty select instruction is which sets lcd driving duty ratio 1/8 or 1/9 or 1/10 duty. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 1 1 0 duty d 2 d 1 d 0 duty ratio scan common 0 0 0 1/8 duty com1 to com8 (5x7 character + 1-icon ) 0 0 1 1/9 duty com1 to com9 (5x7 character + 2-icon ) 0 1 0 1/10 duty com1 to com10 (5x7 character + 3-icon ) (k) power save mode set power save mode reduces the operating current of application using display off and selects a terminal condition of key scan signal output. the terminal, which is set to "l", does not output key scan signal as shown in following table. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 0 0 0 power save key scanning output terminals states *1 d 1 d 0 function internal osc. lcd output s 0 s 1 s 2 s 3 s 4 0 0 normal on on h h h h h 0 1 power save 1 stop display off l l l l h 1 0 power save 2 stop display off l l l h h 1 1 power save 3 stop display off h h h h h *1 no scanning states. (l) general output port pwm phase / freqency set general output port pwm phase / frequency set instruction setting pwm phase and pwm frequency. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 0 1 0 0 phase frequency d 1 general output port pwm phase set 0 32-steps shift phase pwm output timinng by po0 to po1, po1 to po2, po2 to po3. 1 same phase pwm output timinng by po0 to po3. d 0 general output port pwm frequency set 0 fsys / 128 frequency. (default) 1 fsys / 256 frequency. (fsys : system clock = fosc / 2)
- 11 - nju6538 ver.2003-05-09 (m) general output port set. this instruction sets the pwm value outputted from po0 ~ po3 terminals. the ?general output port select? instruction selects the general output port to output with pwm. the ?general output port pwm set? instruction sets the pwm value. the ?general output port select instruction" and the ?general output port pwm set instruction" is not necessary to continuously perform. because these instructions are independently. 1. general output port select. this instruction selects the general output port to output with pwm. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 1 0 0 0 port d 1 d 0 port 0 0 po0 0 1 po1 1 0 po2 1 1 po3 2. general output port pwm set this instruction sets the pwm value outputted from po0 ~ po3 terminals. the pwm output setting is available for 128-step at each port output terminals. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 pwmen pwm 6 pwm 5 pwm 4 0 0 1 1 1 pwm 3 pwm 2 pwm 1 pwm 0 a) pwmen 0:selected general output port is ?l? output. 1:selected general output port outputs pwm depending on pwm data. b) pwm 6 to pwm 0 pwm value:this register sets the duty value of pwm outputted from the selected general output port. the pwm value set requires twice, which are upper 3-bit and lower 4-bit. the pwm duty is (register + 1 ) / 128.
- 12 - nju6538 ver.2003-05-09 (*:don?t care) pwmen pwm 6 pwm 5 pwm 4 pwm 3 pwm 2 pwm 1 pwm 0 pwm duty pwmen pwm 6 pwm 5 pwm 4 pwm 3 pwm 2 pwm 1 pwm 0 pwm duty 0 * * * * * * * 0/128 1 0 0 0 0 0 0 65/128 0 0 0 0 0 0 0 1/128 1 0 0 0 0 0 1 66/128 0 0 0 0 0 0 1 2/128 1 0 0 0 0 1 0 67/128 0 0 0 0 0 1 0 3/128 1 0 0 0 0 1 1 68/128 0 0 0 0 0 1 1 4/128 1 0 0 0 1 0 0 69/128 0 0 0 0 1 0 0 5/128 1 0 0 0 1 0 1 70/128 0 0 0 0 1 0 1 6/128 1 0 0 0 1 1 0 71/128 0 0 0 0 1 1 0 7/128 1 0 0 0 1 1 1 72/128 0 0 0 0 1 1 1 8/128 1 0 0 1 0 0 0 73/128 0 0 0 1 0 0 0 9/128 1 0 0 1 0 0 1 74/128 0 0 0 1 0 0 1 10/128 1 0 0 1 0 1 0 75/128 0 0 0 1 0 1 0 11/128 1 0 0 1 0 1 1 76/128 0 0 0 1 0 1 1 12/128 1 0 0 1 1 0 0 77/128 0 0 0 1 1 0 0 13/128 1 0 0 1 1 0 1 78/128 0 0 0 1 1 0 1 14/128 1 0 0 1 1 1 0 79/128 0 0 0 1 1 1 0 15/128 1 0 0 1 1 1 1 80/128 0 0 0 1 1 1 1 16/128 1 0 1 0 0 0 0 81/128 0 0 1 0 0 0 0 17/128 1 0 1 0 0 0 1 82/128 0 0 1 0 0 0 1 18/128 1 0 1 0 0 1 0 83/128 0 0 1 0 0 1 0 19/128 1 0 1 0 0 1 1 84/128 0 0 1 0 0 1 1 20/128 1 0 1 0 1 0 0 85/128 0 0 1 0 1 0 0 21/128 1 0 1 0 1 0 1 86/128 0 0 1 0 1 0 1 22/128 1 0 1 0 1 1 0 87/128 0 0 1 0 1 1 0 23/128 1 0 1 0 1 1 1 88/128 0 0 1 0 1 1 1 24/128 1 0 1 1 0 0 0 89/128 0 0 1 1 0 0 0 25/128 1 0 1 1 0 0 1 90/128 0 0 1 1 0 0 1 26/128 1 0 1 1 0 1 0 91/128 0 0 1 1 0 1 0 27/128 1 0 1 1 0 1 1 92/128 0 0 1 1 0 1 1 28/128 1 0 1 1 1 0 0 93/128 0 0 1 1 1 0 0 29/128 1 0 1 1 1 0 1 94/128 0 0 1 1 1 0 1 30/128 1 0 1 1 1 1 0 95/128 0 0 1 1 1 1 0 31/128 1 0 1 1 1 1 1 96/128 0 0 1 1 1 1 1 32/128 1 1 0 0 0 0 0 97/128 0 1 0 0 0 0 0 33/128 1 1 0 0 0 0 1 98/128 0 1 0 0 0 0 1 34/128 1 1 0 0 0 1 0 99/128 0 1 0 0 0 1 0 35/128 1 1 0 0 0 1 1 100/128 0 1 0 0 0 1 1 36/128 1 1 0 0 1 0 0 101/128 0 1 0 0 1 0 0 37/128 1 1 0 0 1 0 1 102/128 0 1 0 0 1 0 1 38/128 1 1 0 0 1 1 0 103/128 0 1 0 0 1 1 0 39/128 1 1 0 0 1 1 1 104/128 0 1 0 0 1 1 1 40/128 1 1 0 1 0 0 0 105/128 0 1 0 1 0 0 0 41/128 1 1 0 1 0 0 1 106/128 0 1 0 1 0 0 1 42/128 1 1 0 1 0 1 0 107/128 0 1 0 1 0 1 0 43/128 1 1 0 1 0 1 1 108/128 0 1 0 1 0 1 1 44/128 1 1 0 1 1 0 0 109/128 0 1 0 1 1 0 0 45/128 1 1 0 1 1 0 1 110/128 0 1 0 1 1 0 1 46/128 1 1 0 1 1 1 0 111/128 0 1 0 1 1 1 0 47/128 1 1 0 1 1 1 1 112/128 0 1 0 1 1 1 1 48/128 1 1 1 0 0 0 0 113/128 0 1 1 0 0 0 0 49/128 1 1 1 0 0 0 1 114/128 0 1 1 0 0 0 1 50/128 1 1 1 0 0 1 0 115/128 0 1 1 0 0 1 0 51/128 1 1 1 0 0 1 1 116/128 0 1 1 0 0 1 1 52/128 1 1 1 0 1 0 0 117/128 0 1 1 0 1 0 0 53/128 1 1 1 0 1 0 1 118/128 0 1 1 0 1 0 1 54/128 1 1 1 0 1 1 0 119/128 0 1 1 0 1 1 0 55/128 1 1 1 0 1 1 1 120/128 0 1 1 0 1 1 1 56/128 1 1 1 1 0 0 0 121/128 0 1 1 1 0 0 0 57/128 1 1 1 1 0 0 1 122/128 0 1 1 1 0 0 1 58/128 1 1 1 1 0 1 0 123/128 0 1 1 1 0 1 0 59/128 1 1 1 1 0 1 1 124/128 0 1 1 1 0 1 1 60/128 1 1 1 1 1 0 0 125/128 0 1 1 1 1 0 0 61/128 1 1 1 1 1 0 1 126/128 0 1 1 1 1 0 1 62/128 1 1 1 1 1 1 0 127/128 0 1 1 1 1 1 0 63/128 1 1 1 1 1 1 1 1 128/128 1 0 1 1 1 1 1 1 64/128
- 13 - nju6538 ver.2003-05-09 example ) set output pwm waveform of po0 to po3 terminal, shown below: ? pwm phase set d 1 =0, ? pwmen=1, ? (pwm 6, pwm 5, pwm 4, pwm 3, pwm 2, pwm 1, pwm 0 )=(1,0,0,0,0,0,0) pwm frequency (f pwm ) po0 1 65 66 128 po1 1 65 66 128 po2 1 65 66 128 po3 1 65 66 32-steps 32-steps 32-steps (n) general output port / key scan output select this instruction assigns function of general purpose output port or key scan output to po3/s0 terminals. a0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 0 0 0 d d 0: general output port 1: keyscan output
- 14 - nju6538 ver.2003-05-09 (3) input data format and timing data format is shown below. when the ce terminal goes to ?l?, i/f is data output. when the ce terminal goes to ?h? (rising edge) at scl terminal ?h?, i/f is data input. note1) data fetched at scl rising edge. note2) a contents change of the instruction and data which were written is fetched by the 9th rising edge of scl. note3) when the instruction and data which were written are less than 9-bit, they are ignored and is not fetched. note4) when the instruction and data which were written are over 9-bit, the last 9-bit is valid. (4) power save mode set power save mode is set by ?power save mode set? instruction. the segment and common output "l" is outputted, the osc terminal halts an oscillation (it oscillates at the time of key-on), and consumption current is decreased. power save mode is canceled, when normally set by "power save mode set" instruction. (5) key scan circuit key scan circuit connects the 5 x 5 key-matrix maximum and reads the data of 25 keys maximum. it chooses the number of keys in key-matrix by ?general output port / key scan output select? instruction. it outputs a identified key data to mpu after comparison with two data read from the key-matrix in twice for reliable key operation. if those data are not identified, key data is not outputted. it outputs ?l? signal through ?so? terminal as the request after 332t[s] (t=1/fsys=2/fosc,fsys : internal system clock frequency) when any key is operated. furthermore, the key scan circuit structures for reducing the external components like as diodes to prevent circuit short problem. (5-1) the relation between output data and key matrix the relation between output data and key matrix shows bellow table and sets ?1? signal for operated key. in case of 20 keys application, unassigned area for keys from kd1 to kd5 in bellow table take ?0? signal. in mode of power save 1, area for keys from kd1 to kd20 in bellow table take ?0? signal. in mode of power save 2, area from kd1 to kd15 take ?0? signal also. the terminals, which are not connected any keys, should be open. k 0 k 1 k 2 k 3 k 4 s 0 kd1 kd2 kd3 kd4 kd5 s 1 kd6 kd7 kd8 kd9 kd10 s 2 kd11 kd12 kd13 kd14 kd15 s 3 kd16 kd17 kd18 kd19 kd20 s 4 kd21 kd22 kd23 kd24 kd25 * d7 d6 d5 d4 d3 d2 d1 d0 a0 * ce sio scl output input output sio state
- 15 - nju6538 ver.2003-05-09 (5-2) data output timing the data output format shows bellow. the data output mode is set by ?l? status of scl terminal at the rising signal of ce terminal. (5-3) power save flag (psf) the status of power save flag is outputted after kd25 in key data reading. this flag sets ?1? signal in mode of power save in key data reading and sets ?0? in mode of normal. (5-4) timing of key scan key scan cycle is 160t[s] (t=1/fsys=2/fosc,fsys : internal system clock frequency). the data of key scan is a result of comparison with a couple of key scan for correct judge whether key on or off. when the result of comparison is correct (accord), the nju6538 recognizes key on and outputs ?l? level from sio terminal after 322t[s] from start of key scan for a request to read key data out to external mpu. when the sio terminals outputs ?l? signal, the key scan does not operate until end of key data reading by mpu, and scanned key data is kept. when the result of comparison is incorrect (not accord), key scan operates again if any key is on. therefore, key scan may operate incorrectly in case of shorter period of key on than 322t[s] *1 instruction set the general output ports or output the key scan signals (refer (1)instruction (n)general output port / key scan select) key scan cycle and the timing of key data read out request are constant in any power save mode. output output output * kd1 kd2 kd24 kd25 psf key data ce scl sio t=1/fsys =2/fosc ( fsys : internal system clock frequency ) s 0 s 1 s 2 s 3 s 4 sio 1 1 *1 *1 2 2 *1 *1 3 3 *1 *1 4 4 *1 *1 5 5 *1 *1 322t [s] 160t[s] key on sio state
- 16 - nju6538 ver.2003-05-09 (5-5) normal mode key scan operates with follows in normal mode. 1, key scan signal output terminals s0 ? s4 output ?h? signals when key scan does not operate, and output key scan signals after start of key scan operation. the conditions of key scan signal input terminals k0 ? k4 are ?l? state with internal pull-down resistances, though ?h? signal comes in to k0 ? k4 corresponding to the turned on keys. 2, the function of key scan starts twice operations when any key is turned on. it stops when a couple of data by continuously twice key scan operations are accorded and fixed as a correct key status. it operates more 2 times when the key status is not fixed and any keys are still turning on. it repeats again and again until key status is fixed. the correct key status data is stored and newly key scan operation does not start until external mpu reads data out after key status is fixed. 3, when the key status is fixed, so terminal outputs ?l? signal as key data read out request to mpu. mpu should read key data out at detection of this ?l? signal. 4, the key data read out request signal is released and so terminal outputs ?h? signal after finish of mpu key data read out for newly key scan operation. sio terminal requires pull up resistor because of open drain type output. multiple data of key are output in case of key more input so that mpu should process the data by itself. key scan example (normal mode) so key data read request key data read key data read request key data read key data read t = 1 / fosc ce key input 1 key input 2 data send si key scan 322t[s] 322t[s] 322t[s] scl data send data send key data read request
- 17 - nju6538 ver.2003-05-09 (5-6) power save mode key scan operates with follows in power save mode. 1, key scan signal output terminals s0 ? s4 output ?h?, ?l? signals by the power save mode set when key scan does not operate (refer the detail of instructions), and output key scan signals after start of key scan operation. the conditions of key scan signal input terminals k0 ? k4 are ?l? state with internal pull-down resistances, though ?h? signal comes in to k0 ? k4 corresponding to the turned on keys. 2, the oscillation circuit function of key scan starts twice operations when any keys on cross points with s0? s4 terminals line and k0 ? k4 turned on. it stops when a couple of data by continuously twice key scan operations are accorded and fixed as a correct key status. it operates more 2 times when the key status is not fixed and any keys are still turning on. it repeats again and again until key status is fixed. the correct key status data is stored and newly key scan operation does not start until external mpu reads data out after key status is fixed. 3, when the key status is fixed, sio terminal outputs ?l? signal as key data read out r equest to mpu. mpu should read key data out at detection of this ?l? signal. 4, the key data read out request signal is released and sio terminal outputs ?h? signal after finish of mpu key data read out for newly key scan operation. although power save mode is not released. sio terminal requires pull up resistor because of open drain type output. multiple data of key are output in case of key more input so that mpu should process the data by itself. key scan example (power save mode) ex.) d0= ?0?, d1= ?1? (k4=?h? power save) *1 these diodes are required to recognize key more input of keys on the k4 line when only k4 terminal outputs ?h? signal in power save mode as shown above example. in case of no diodes, incorrect key data may read out sometimes by key more input of keys on lines of k0 to k4. t=1/fsys =2/fosc ( fsys : internal system clock frequency ) when some key on these lines are turned on, the oscillation starts and key scan starts the operation until all of key are turned off. *1 s 0 ?l? s 1 ?l? s 2 ?l? s 3 ?l? s 4 ?h? k 0 k 1 k 2 k 3 k 4 data send data send data send si key input (k4) key scan 322t[s] 322t[s] ce scl so key data read request key data read key data read request key data read t = 1 / fosc
- 18 - nju6538 ver.2003-05-09 (5-7) key more input key scan signal output terminal s0 to s4 output ?h? level in state of key more input. although key state is detected without diodes to prevent unexpected key scan signal flow, non-pressed key data may change pressed key data in triple or more key input as shown in fig. 1 and incorrect key data may be output to external mpu. for prevention of miss-recognition by incorrect key data, diodes should be inserted in front of k0 ? k4 terminals as shown in fig. 3 or control program of mpu should ignore the combination of key data miss-recognition. for example, 4 keys and more on data should be ignored. fig. 1 miss-recognized example by key more input in modes of power save 1 (s0=0, s1=1 / keys on only s5 line are valid) or power save 2 (s0=0, s1=1 / keys on only s4 and s5 lines are valid), pay attention about the followings. when key more input is operated across the valid line and invalid, non-pressed key is miss-recognized as pressed key. however, key data on the invalid line is not read out and 4 keys and more operation in the mean time are not ignored by mpu control program as shown in fig. 2. in this case, diodes operate to prevent miss-recognition as shown in fig. 3. fig. 2 miss-recognition in power save 1 fig. 3 connect miss-recognition prevent diodes s 0 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k4 pressed key miss-recognized key in case of 3 keys operation in lef t picture, if s3 terminal outputs ?h? signal, this signal goes around on the dotted line and non-pressed key is miss-recognized as pressed key. in case of power save 1, mpu control program can no t decide ether correct key data or incorrect as shown above because key data on only s4 line is read out to mpu ( all of ke y data on s3 line become to ?0?. s 0 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k 4 pressed key miss-recognized key miss-recognition prevent diodes s 0 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k 4 no active key active key
- 19 - nju6538 ver.2003-05-09 (5-8) key data reading out operation by external mpu (a) display data writing display data and an instruction change operate at the rising edge of 9-bit on scl signal. (b) key data reading out operation the minimum period from key in to sio terminal = ?l? is 322t(t1) by key scan operation. when key scan operation performs again for key data fix preventing from noise or bouncing of key, the period from key in to sio terminal = ?l? is 676t(t1). when the sio terminal outputs ?l?, the key scan operation is stopped after execution of key data reading out operation. therefore, fixed key data is kept until end of key data reading out operation. when key data reading out operation is performed during so terminal = ?h?, both of key data from kd1 to kd25 and power save flag (psf) are not outputted correctly. key data reading out operation example the flowchart below shows an example of timer interrupt application. when sio terminal condition is ?l? after check of sio terminal condition at every timer interrupt operation, it is decided as key in and key data reading out operation is performed. when sio terminal condition is ?h, it is decided as key off. for the correct decision of key off, the timer interrupt cycle (1/t3) should be expanded over the time added with [period of key scan (676t in case of measure against key bouncing of key) and [period of key data reading out operation (t2)]. in this time, the period of timer interrupt cycle (t3) must be set with enough margins including the range of fosc. sequence of key data reading out operation timer so=?l?? key off key on key data read out end of timer yes no
- 20 - nju6538 ver.2003-05-09 timing chart of key data reading out operation (6) reset circuit initializes reset circuit initializes the nju6538 at power on and off. it generates reset signal to initialize the system at low vdd less than power down detection voltage (2.0v typical). (6-1) initial status in reset 1, stop the oscillation circuit 2, display off (available serial data transmission) 3, disable key scan function 4, filled ?l? ? data in all of key data buffer (6-2) the status of output port terminals in reset *1 this terminal operates as segment driver and outputs ?l?. *2 this terminal consisted of open-drain output type circuit requires external pull-up resister connect ting to external power source for mpu. i f key data read is executed in power on reset, the read data is fixed as ?h?. the reset circuit initializes the lsi to the following status by using of the input 10 s(min.) or over ?l? level signal into the resb terminal. the lsi will return to normal operation after about 1.0 s(max.) from the rising edge of the rest signal. the ?reset? instruction can?t be substituted for the reset operation by using of the resb terminal. it executes above-mentioned only 7 to 13 items. output terminals reset status seg 1 to seg 65 l com 1 to com 10 l po0 to po2 l po3/s 0 l *1 s 1 to s 4 h sio h *2 t1: key scan time t2: key data read time t3: interrupt cycle *: t3 > t1 + t2 key input so ce decision interrupt scl key on t1 t2 t2 t1 key on key off key off t3 t3 t3 key off t3 t1
- 21 - nju6538 ver.2003-05-09 (6-3) reset status using the resb terminal (default) 1. serial interface register clear 2. display off 3. adc select : d 0 =?0? (normal mode) 4. normal display (non-inverse display) 5. whole display off : d 0 =?0? (normal mode) 6. power save mode : d 1 , d 0 =?0, 0? (normal mode) 7. page address : 0 page 8. column address : 00 h 9. evr register : d 3 , d 2 , d 1 , d 0 =?1, 1, 1, 1? 10. duty select : 1/10 duty 11. general output port pwm phase and frequency : d 1 , d 0 =?0, 0? 12. general output port : pwmen=0 (?l? output), pwm value : d 6 , d 5 , d 4 , d 3 , d 2 , d 1 , d 0 =?0, 0, 0, 0, 0, 0, 0? 13. po3/s0 terminal : d 0 =? 0? (po3) (6-4) initialization by hardware the nju6538 incorporates reset terminal to initialize the all system. when the ?l? level signal input over then 10us(min.) to the resb terminal, reset sequence is executed. in this time, internal busy during 1us after resb terminal goes to ?h?. reset circuit (6-5) power on reset operation when the voltage rising time of power source is over than 1ms, the generated signal of vdet initializes the system of nju6538 as reset. when the voltage falling time of power source is over t han 1ms, the system is also reset. when these voltage rising or falling time of power source are not over than 1ms, the initialization operation as reset does not operate correctly. vdet t on > 1 ms v dd v dd > 2.7v t off > 1 ms vdet power on reset hardware reset system reset resb
- 22 - nju6538 ver.2003-05-09 (7) lcd panel drive (7-1) lcd driving voltage generation circuit lcd driving voltage generation circuit generates lcd driving bias voltages v lcd2 , v0, v1 and v2. it adjusts the voltage by 8 steps electrical volume from v lcd1 and allots the voltage to v lcd2 , v0, v1 and v2 by resistor-voltage-dividing as shown in below. vlcd1, vlcd2, v0, v1 and v2 terminals requires external capacitors for bias voltage stabilization for display quality. these values of capacitors should be fixed in accordance with evaluation in the application. duty ratio 1/8,1/9,1/10 power supply bias 1/4 v lcd v lcd2 -v ss note 1 : resistor is typical value. + + + + v lcd2 v 0 v 1 v 2 v ss internal nju6538 10k ? ( note 1 ) e.v.r. (16-steps) vlcd 10k ? ( note 1 ) 10k ? ( note 1 ) 10k ? ( note 1 ) v lcd1 10k ? ( note 1 ) +
- 23 - nju6538 ver.2003-05-09 absolute maximum ratings ta=25 c parameter symbol conditions ratings unit vdd max v dd terminal -0.3 to +7.0 supply voltage vlcd max v lcd1 terminal -0.3 to +11.0 v v in1 osc, k 0 to k 4 ,ce, scl, sio terminal -0.3 to vdd+0.3 input terminal voltage v in2 v lcd2, v 0 to v 2 terminal -0.3 to vlcd+0.3 v v out1 sio terminal -0.3 to +6.0 output terminal voltage v out2 osc, seg 1 to seg 65 ,com 1 to com 10 , s 1 to s 4 , po 0 to po 2, po 3 /s 0 terminal -0.3 to vdd+0.3 v ta=25 c qfp100-c2 1000 power dissipation pdmax ta=25 c qfp100-g1 700 mw storage temperature tstg - -55 to +125 c operating temperature topr - -40 to +85 c note 1) all voltage values are specified as v ss =0v. note 2) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. note 3) decoupling capacitor should be connected between vdd and vss due to the stabilized operation forthe voltage converter.
- 24 - nju6538 ver.2003-05-09 dc electrical characteristics vdd=2.7 to 5.5v, ta= - 40 to 85 c parameter symbo l condition min typ max unit not e power supply (1) vdd vdd 2.7 5.5 power supply (2) vlcd1 vlcd1 5.0 10.0 v output voltage vlcd2 vlcd2 4.0 vlcd1 v v0 v0 vss vlcd2x3/4 vlcd2 v1 v1 vss vlcd2x2/4 vlcd2 input voltage v2 v2 vss vlcd2x1/4 vlcd2 v 1 ?h? level input voltage (1) vih(1) k 0 to k 4 0.6vdd vdd v ?h? level input voltage (2) vih(2) scl, sio, ce 0.8vdd vdd v ?l? level input voltage (1) vil(1) k 0 to k 4 , scl, sio, ce 0 0.2vdd v hysteresis voltage vh scl, sio, ce 0.25vdd v ?h? level input current i ih scl, sio, ce, v in = vdd 5.0 a ?l? level input current i il scl, sio, k 0 to k 4 , ce, v in = 0v -5.0 a pull-up resistance r pu resb vdd=5.0v, v in = 0v 50 150 250 k ? pull-down resistance r pd k 0 to k 4 , vdd=5.0v, v in = vdd 50 150 250 k ? output off-leak current ioffh sio, vo=5.5v 6.0 a vdd=5.0v, io = -500ua vdd-1.2 vdd-0.2 ?h? level output voltage (1) voh(1) s 0 to s 4 vdd=3.0v, io = -250ua vdd-1.1 vdd-0.1 v vdd=5.0v, io = -10ma vdd-1.0 ?h? level output voltage (2) voh(2) po 0 to po 3 vdd=3.0v, io = -5ma vdd-0.6 v vdd=5.0v, io = 25 a 0.2 1.5 ?l? level output voltage (1) vol(1) s 0 to s 4 vdd=3.0v, io = 5 a 0.05 0.6 v vdd=5.0v, io = 10ma 1.0 ?l? level output voltage (2) vol(2) po 0 to po 3 vdd=3.0v, io = 5ma 0.6 v ?l? level output voltage (3) vol(3) sio io = 1ma 0.5 v driver on-resistance (com) r com ta = 2 5 c , vo=v lcd2 ,vss,v0,v2 + id=1 a (com terminal) 40 k ? 2 driver on-resistance (seg) r seg ta = 2 5 c , vo=v lcd2 ,vss,v1 + id=1 a (seg terminal) 40 k ? 2 oscillation frequency f osc ta = 2 5 c , vdd=5.0v r osc =150k ? 38 50 62 khz v0 5.8 6.0 6.2 v1 3.8 4.0 4.2 lcd driving voltage v2 e.v.r. value ?0,0,0,0? v lcd1 =8.0v 1.8 2.0 2.2 v bleeder resistance r b vlcd2-vss, ta=25 c 40 k ? e.v.r. resistance r evr vlcd1-vlcd2, ta=25 c 10 k ? power down detect voltage vdet 0.8 1.4 2.0 v reset time tr resb 1.0 s reset ?l? pulse width trw resb 10.0 s idd1 power save mode 100 a idd2 vdd=5.5v, output open f osc =50khz, 500 a ilcd1 power save mode 5 a operating current ilcd2 vlcd1=10.0v output open f osc =50khz, 1000 a note 1) the relation : vlcd1 vlcd2 v0 v1 v2 vss must be maintained. note 2) rcom and rseg are the resistance values between power supply terminals (vss, vlcd2, or v0, v1, v2) and each common terminal, and supply voltage (vss, vlcd2, or v0, v1, v2) and each segment terminal respectively, and measured when the current id is flown on every common and segment terminals at a same time.
- 25 - nju6538 ver.2003-05-09 ac characteristics vdd=2.7 to 5.5v, ta= - 40 to 85 c parameter symbol condition min typ max unit note ?l? level clock pulse width t wcll scl 160 ns ?h? level clock pulse width t wclh scl 160 ns data setup time t ds scl, sio 160 ns data hold time t dh scl, sio 160 ns ce wait time t cp ce, scl 160 ns ce setup time t cs ce, scl 160 ns ce hold time t ch ce, scl 160 ns ce ?l? level width t wcl ce 160 ns sio output delay time t dc sio, rpu=4.7k ? , cl=10pf 1.5 s sio rise time t dr sio, rpu=4.7k ? , cl=10pf 1.5 s 1 scl rise tine t r 15 ns scl fall time t f 15 ns so terminal is open-drain type output, so that the characteristics of so terminal are changed by values of pull-up resistance rpu and cl. (1) write operation (2) key data read operation scl ce sio t cp t wclh t wcll t r t f t dc t dr t cs t ch d 0 scl ce sio t wcll t wclh t f t r t ds t dh t cs t cp t ch d 0 d 1 t wcl invalid
- 26 - nju6538 ver.2003-05-09 relation between oscillation frequency and lcd frame frequency (1)1/8 duty ex.)fosc=50khz frame frequency =1/(40t x duty)=1/(40 x (2/50khz) x 8)=78.1(hz) (2)1/10 duty fosc=50khz frame frequency =1/(35t x duty)=1/(35 x (2/50khz) x 10)=71.4(hz) com1 v ss segn 1 2 3 4 8 1 2 3 4 81 2 3 v lcd2 v 0 v 1 v 2 v ss 1frame 1frame 1 line select time(40 t[s]) v lcd2 v 0 v 1 v 2 56 5 7 6 7 1 2 3 4 8 1 2 3 4 8 1 2 3 56 5 7 6 7 on off com1 v ss segn 1 2 3 4 8 1 2 3 4 81 23 v lcd2 v 0 v 1 v 2 v ss 1frame 1frame 1 line select time(35 t[s]) v lcd2 v 0 v 1 v 2 5 6 5 7 6 7 1 2 3 4 8 1 2 3 4 8 1 2 3 5 6 5 7 6 7 9 10 9 10 9 10 9 10 on off t = 1/fsys = 2/fosc ( fsys : internal system clock frequency ) t = 1/fsys = 2/fosc ( fsys : internal system clock frequency )
- 27 - nju6538 ver.2003-05-09 application circuit *1 the rising time of power source voltage at power on and the falling time at power off must keep over than 1ms because of voltage detection type reset circuit operation. *2 so terminal requires external pull-up resistor connecting to power source of external mpu because of open-drain type output. *3 this capacitor for bias voltage stabilization should be connected in accordance with display quality in application. *4 p o3 / s 0 terminal is general output ports and key scan signal output duplicated-function terminals. a function must be selected either segment output or other. *3 com 1 po 3 /s 0 s 1 s 2 s 3 s 4 k 0 k 1 k 2 k 3 k 4 mpu resb ce sc sio v lcd1 v lcd2 v 0 v 1 v 2 v ss po 0 po 1 po 2 po 3 /s 0 *2 general output ports *3 *3 *3 *3 nju6538 5 x5 key matrix *4 v lcd v ss ---- com 10 seg 1 ---- seg 65 7com 65seg matrix +195 icon lcd panel osc v dd v ss *1 v dd v ss [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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